1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor devices such as insulated gate electrostatic induction type transistors, vertical MOS semiconductor devices utilizing an accumulation layer, etc.
2. Description of the Prior Art
It is possible to consider a construction such that insulated gate electrostatic induction type transistors can be obtained by replacing conventional junction gates with insulated gates, as shown in FIG. 1(A), which comprises an n.sup.- drain region 1, n.sup.+ source regions 2, gate electrodes 3, gate insulating films 4, and interlayer insulating films 5. The drain region 1 is ohmically connected to a drain electrode 11. The drain region 1 and the source regions 2 are insulated from the gate electrodes 3 by the gate insulating films 4, respectively. A source electrode 22 is ohmically contacted to source regions 2, and also formed on the interlayer insulating films 5. Here, the drain between the two adjacent insulated gates 4 is called "channel" in the device structure, and a distance between the two insulated gates 4 designated by H is called "channel range thickness". In the above structure, current is cut off by a depletion layer developed in the vicinity of the insulated gate 4. However, in the case of the insulated gate, being different from the junction gate, there exists a limit in the width of the depletion layer developed by forming the accumulation layer of minor carrier in the vicinity of the insulated gate 4. Therefore, there exists a limitation with respect to the relationship between the impurity atom concentration N.sub.D within the channel range and the thickness H of the channel range as expressed by the following formula: ##EQU1## where q denotes the electron charge; .epsilon. denotes the dielectric constant of the semiconductor of the drain region; .phi..sub.f denotes the absolute Fermi potential value of the semiconductor expressed as ##EQU2## where k denotes the Boltzmann constant; T denotes the absolute temperature; and Ni denotes the intrinsic carrier concentration of the drain region semiconductor.
The above formula indicates that the channel range thickness H is less than twice the developable depletion width of one of the insulated gate. When H exceeds the right side in the above formula; it is impossible to cut off the current, even if a high voltage is applied to the gate.
By way of example, in the case of silicon semiconductor, the required channel range thickness is 4.8 .mu.m or less when the impurity atom concentration of the drain region is 1.times.10.sup.- cm.sup.-3, and 1.7 .mu.m or less when the impurity atom concentration is 1.times.10.sup.15 cm.sup.-3. Therefore, when a higher impurity atom concentration is required to some extent as in the case of low voltage resistant devices, it is practically impossible to form such a microstructure as described above.
On the other hand, a prior-art MOS semiconductor device utilizing an accumulation layer is disclosed in Japanese published Unexamined (Kokai) Patent Appli. No. 55-108768 entitled "Electrostatic Induction Thyristor", as shown in FIG. 1(B). In the drawing, the semiconductor device comprises an n.sup.- drain region 1, a p.sup.+ region 20, n.sup.+ source regions 2. The drain electrode 11 is ohmically connected to the p.sup.+ region 20. A gate electrode 3 is insulated from the drain region 1 and the source region 2 by a gate insulating film 4. The thickness of the film 4 opposing the drain electrode 11 is large to increase the voltage-resistant characteristics. A source electrode 22 is ohmically connected to the source region 2. Further, in FIG. 1(B), although two and half unit structures in each of which is composed of an insulated gate 4 and a source region 2 are shown, in practice a plurality of unit structures are arranged in parallel within an single chip.
The portion sandwiched between the two insulated gates 4 within the drain region 1 is called "channel" of the device structure; the distance between two insulated gates 4 represented by H is called "thickness of channel range"; and the symbol L is called "channel length". Further, since the above document is a thyristor patent, the p.sup.+ region 20 is included in the structure shown in FIG. 1(B) so as to provide a bipolar element.
On the other hand, in a semiconductor device realized by the manufacturing method of the present invention as described later, no p.sup.+ region 20 is disclosed because of a unipolar element. However, the structure of the source regions and the gate electrodes is the same, and therefore the presence or absence of the p.sup.+ region 20 will not exert any influence upon the function and the structure thereof.
The operation of the above-mentioned MOS semiconductor element utilizing the above accumulation layer will be described hereinbelow.
The source electrode 22 is grounded, and a positive voltage is applied to the drain electrode 11. Under these conditions, when the gate electrode 3 is grounded or a negative potential is applied to the gate electrode 3 to develop a depletion layer in the channel range, conductive electrons can not flow out of the source region 2, so that current is cut off. Further, when a negative potential is removed from the gate electrode to remove the depletion layer in the channel range or when a positive potential is applied to the gate electrode to form electron accumulative layer in the vicinity of the insulated gate, the source region is conductive to the drain region to allow a main current to flow. Once the accumulation layer is formed in the vicinity of the insulated gate, since the conductivity of the accumulation layer is high, the resistance of the channel range is reduced and therefore disregarded, as compared with the drift resistance of the drain region.
Further, in the above structure, if conductive electrons are emitted from the source region 2, since positive holes of the minor carrier are injected from the p.sup.+ region 20 on the drain side, the resistance of the n.sup.- drain region 1 is further reduced on the basis of conductivity modulation effect.
In the above-mentioned structure, however, the channel structure is restricted as follows: Although the main current is cut off by the depletion layer developed in the vicinity of the insulated gate as already described, in the case of insulated gate, being different from the junction gate, since an inversion layer of the minor carrier is formed in the vicinity of the gate insulating film, there exists a limit in the width of the developable depletion layer. That is, the impurity atom concentration N.sub.D of the channel range and the thickness H of the channel range are also restricted in accordance with the afore-mentioned formula.
To overcome the above-mentioned "Limitation of Channel Range Thickness", Japanese Published Examined (Kokoku) Patent Appli. No. 62-44698 or (Kokai) Patent Appli. No. 55-85069 has disclosed "Insulated Gate Transistor", in which additional fixed-potential control gates are provided in the vicinity of driving U-shaped insulated gates, respectively to control the various device characteristics on the basis of the potential of the control gates. The fixed potential control gates are of pn-junction gates, Schottky gates or insulated gates of other types.
FIG. 2(A) shows a prior-art device structure where the control gates 6 fixed to the source electrode 22 are formed in the form of junction gates. This device comprises an n.sup.- drain region 1, n.sup.+ source regions 2, gate electrodes 3, gate insulating films 4, interlayer insulating films 5, and p-type control gates 6. A drain electrode 11 is ohmically connected to the drain region 1. The drain region 1 and the source regions 2 are insulated by the gate insulating films 4. The source electrode 22 is electrically connected to the p-type control gates 6 and the source regions 2. In this device structure, when the impurity atom concentration of the p-type control gate 6 is high, since the built-in depletion layer is developed mainly in the n.sup.- drain region 1, it is possible to electrically cut off the channel range (the drain region sandwiched between two different types of gates) in dependence upon the depletion layer developed in the gate electrode, beyond the limitation defined by the afore-mentioned formula. The current conduction between the drain region and the source region can be attained on the basis of the accumulation layer formed in the vicinity of the insulated gate in the same way as in the prior-art devices. Further, FIG. 2(B) shows another method in which each control gate is connected to a control gate terminal 66 to apply a negative fixed potential thereto.
The above-mentioned control gates 6 as shown in FIGS. 2(A) and 2(B) can be generally formed by selectively injecting and diffusing p-type impurity ions into between the insulated gates 4 by photoprocess as shown in FIG. 2(C). In FIG. 2(C), the reference numeral 100 denotes a resist and 600 denotes a range where p-type impurity atoms are ion-injected. Further, FIG. 2(D) shows another method in which a groove is formed in a specific range between the two insulated gates 4 by photoprocess to diffuse p-type impurity atoms into the groove inside. Further, it is also possible to bury a metal in the groove so as to be Schottky junctioned to the n.sup.- substrate 1.
In the above-mentioned prior-art methods, there exist two serious problems as follows: The first problem relates to the dispersion of the device threshold value (turn-on voltage). That is, when a photomask for forming the control gates is mismatched, the threshold value of channel range becomes different between both the sides of the control gate 6, and therefore the device characteristics are not uniform.
The second problem relates to pattern microstructure or fine structure to increase the device current capacity. With the first problem in mind, it is necessary to set the channel range size to such a large degree as 5 to 10 times the mask matching precision of the photodevice. This is indispensable when the control gates are formed by photoprocess. For example, where such a photodevice that the minimum formable pattern size is 3 .mu.m and the matching precision is 0.5 .mu.m is used, the minimum unit in the device structure is about 6 to 8 .mu.m, which is the pattern size limitation.
As described above, in the first prior-art structure as shown in FIGS. 1(A) and 1(B), there exists a limitation in channel thickness within which the channel range can be cut off, so that it has been difficult to apply the first prior-art structure to low-voltage resistant device having a high impurity atom concentration in the channel range.
Further, in the second prior-art structure as shown in FIGS. 2(A), 2(B) and 2(D), although it is possible to avert the problem related to the first prior-art structure, there still exists a limitation in photoprocess precision when the pattern microstructure is required to allow the threshold value to be uniform or to increase the entire current capacity.